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? semiconductor components industries, llc, 2009 december, 2009 ? rev. 0 1 publication order number: amis ? 30522/d amis-30522, NCV70522 micro-stepping motor driver introduction the amis ? 30522/NCV70522 is a micro ? stepping stepper motor driver for bipolar stepper motors. the chip is connected through i/o pins and a spi interface with an external microcontroller. the amis ? 30522/NCV70522 contains a current ? translation table. it takes the next micro ? step depending on the clock signal on the ?nxt? input pin and the status of the ?dir? (= direction) register or input pin. the chip provides a so ? called ?speed and load angle? output. this allows the creation of stall detection algorithms and control loops based on load ? angle to adjust torque and speed. it is using a proprietary pwm algorithm for reliable current control. the amis ? 30522/NCV70522 is implemented in i 2 t100 technology, enabling both high voltage analog circuitry and digital functionality on the same chip. the chip is fully compatible with the automotive voltage requirements. the 522 is ideally suited for general purpose stepper motor applications in the automotive, industrial, medical and marine environment. the amis ? 30522 is intended for use in industrial applications. the NCV70522 vers ion is qualified for use in automotive applications. features ? dual h ? bridge for 2 phase stepper motors ? programmable peak ? current up to 1.2 a continuous (1.5 a short time), using a 5 ? bit current dac ? on ? chip current translator ? spi interface ? speed and load ? angle output ? 7 step modes from full ? step up to 32 micro ? steps ? fully integrated current ? sense ? pwm current control with automatic selection of fast and slow decay ? low emc pwm with selectable voltage slopes ? active fly ? back diodes ? full output protection and diagnosis ? thermal warning and shutdown ? digital io?s compatible with 5 v and 3.3 v microcontrollers ? integrated 5 v voltage regulator to supply an external microcontroller ? integrated reset function to reset external microcontroller ? integrated watchdog function ? ncv prefix for automotive and other applications requiring site and control changes ? these are pb ? free devices* *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. http://onsemi.com see detailed ordering and shipping information in the package dimensions section on p age 27 of this data sheet. ordering information 1 2 3 5 4 6 7 8 24 23 22 20 21 19 18 17 9 10111213141516 32 31 30 29 28 27 26 25 di gnd gnd motyn clk dir nxt sla gnd gnd gnd motyn motxn motxn err cpn cpp vcp clr vbb motyp motyp cs vdd do tsto vbb motxp motxp pinout amis ? 30522/ NCV70522 por /wd
amis ? 30522, NCV70522 http://onsemi.com 2 table of contents page introduction 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . features 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . block diagram 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pin description 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . absolute maximum ratings 4 . . . . . . . . . . . . . . . . . . . . . . . . . equivalent schematics 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . package thermal characteristics 5 . . . . . . . . . . . . . . . . . . . . thermal resistance 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . electrical specification 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . recommended operation conditions 5 . . . . . . . . . . . . . . . . dc parameters 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ac parameters 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . spi timing parameters 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . typical application schematic 10 . . . . . . . . . . . . . . . . . . . . . . functional description 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . warning, error detection and diagnostics feedback 18 . . spi interface 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ordering information 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . package outline 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
amis ? 30522, NCV70522 http://onsemi.com 3 figure 1. block diagram amis ? 30522/NCV70522 tst0 gnd motxn motyp motyn clk di do nxt dir sla clr timebase charge pump logic & registers load angle temp. sense band ? gap otp por spi i ? sense emc i ? sense emc pwm amis ? 30522/NCV70522 pwm translator cpn cpp vcp vbb cs err motxp por /wd vreg vdd table 1. pin description name pin description type equivalent schematic gnd 1 ground supply di 2 spi data in digital input type 2 clk 3 spi clock input digital input type 2 nxt 4 next micro ? step input digital input type 2 dir 5 direction input digital input type 2 err 6 error output (open drain) digital output type 4 sla 7 speed load angle output analog output type 5 / 8 no function (to be tied to ground) cpn 9 negative connection of charge pump capacitor high voltage cpp 10 positive connection of charge pump capacitor high voltage vcp 11 charge ? pump filter ? capacitor high voltage clr 12 ?clear? = chip reset input digital input type 1 cs 13 spi chip select input digital input type 2 vbb 14 high voltage supply input supply type 3 motyp 15, 16 positive end of phase y coil output driver output gnd 17, 18 ground supply motyn 19, 20 negative end of phase y coil output driver output motxn 21, 22 negative end of phase x coil output driver output gnd 23, 24 ground supply motxp 25, 26 positive end of phase x coil output driver output vbb 27 high voltage supply input supply type 3 por /wd 28 power on reset and watchdog reset output digital output type 4 tst0 29 test pin input (to be tied to ground in normal operation) digital input / 30 no function (to be tied to ground) do 31 spi data output (open drain) digital output type 4 vdd 32 logic supply output (needs external decoupling capacitor) supply type 3
amis ? 30522, NCV70522 http://onsemi.com 4 table 2. absolute maximum ratings symbol parameter min max unit v bb analog dc supply voltage (note 1) ? 0.3 +40 v t st storage temperature ? 55 +160 c t j junction temperature (note 2) ? 50 +175 c v esd electrostatic discharges on component level, all pins (note 3) ? 2 +2 kv v esd electrostatic discharges on component level, hiv pins (note 4) ? 8 +8 kv stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. for limited time < 0.5 s 2. circuit functionality not guaranteed. 3. human body model (100 pf via 1.5 k , according to jedec eia ? jesd22 ? a114 ? b) 4. hiv = high voltage pins motxx, v bb , gnd; human body model (100 pf via 1.5 k , according to jedec eia ? jesd22 ? a114 ? b) table 3. thermal resistance package thermal resistance unit junction ? to ? exposed pad junction ? to ? ambient 1s0p board 2s2p board nqfp ? 32 0.95 60 30 k/w equivalent schematics the following figure gives the equivalent schematics of the user relevant inputs and outputs. the diagrams are simplified representations of the circuits used. figure 2. in ? and output equivalent diagrams in in vdd out sla 4k 4k vbb vdd vbb r out type 1: clr input type 2: clk, di, cs , nxt, dir inputs type 4: do and err open drain outputs type 5: sla analog output type 3: v dd and v bb power supply rpd
amis ? 30522, NCV70522 http://onsemi.com 5 package thermal characteristics the 522 is available in a nqfp32 package. for cooling optimizations, the nqfp has an exposed thermal pad which has to be soldered to the pcb ground plane. the ground plane needs thermal vias to conduct the heat to the bottom layer. figure 3 gives an example for good power distribution solutions. for precise thermal cooling calculations the major thermal resistances of the device are given. the thermal media to which the power of the devices has to be given are: ? static environmental air (via the case) ? pcb board copper area (via the exposed pad) the thermal resistances are presented in table 5: dc parameters. the major thermal resistances of the device are the rth from the junction ? to ? ambient (rthja) and the overall rth from the junction ? to ? exposed pad (rthjp). in the table below one can find the values for the rthja and rthjp, simulated according to jesd ? 51: the rthja for 2s2p is simulated conform jedec jesd ? 51 as follows: ? a 4 ? layer printed circuit board with inner power planes and outer (top and bottom) signal layers is used ? board thickness is 1.46 mm (fr4 pcb material) ? the 2 signal layers: 70 m thick copper with an area of 5500 mm 2 copper and 20% conductivity ? the 2 power internal planes: 36 m thick copper with an area of 5500 mm 2 copper and 90% conductivity the rthja for 1s0p is simulated conform jedec jesd ? 51 as follows: ? a 1 ? layer printed circuit board with only 1 layer ? board thickness is 1.46 mm (fr4 pcb material) ? the layer has a thickness of 70 m copper with an area of 5500 mm 2 copper and 20% conductivity ?????????? ?????????? ?????????? ?????????? figure 3. example of nqfp ? 32 pcb ground plane layout in top view (preferred layout at top and bottom) nqfp ? 32 electrical specification recommended operation conditions operating ranges define the limits for functional operation and parametric characteristics of the device. note that the functionality of the chip outside these operating ranges is not guaranteed. operating outside the recommended operating ranges for extended periods of time may affect device reliability. table 4. operating ranges symbol parameter min max unit v bb analog dc supply +6 +30 v v dd logic supply output voltage 4.75 5.25 v t j junction temperature ? 40 +172 (note 5) c 5. no more than 100 cumulative hours in life time above t tw
amis ? 30522, NCV70522 http://onsemi.com 6 table 5. dc parameters (the dc parameters are given for v bb and temperature in their operating ranges unless otherwise specified) convention: currents flowing in the circuit are defined as positive. symbol pin(s) parameter remark/test conditions min typ max unit supply inputs v bb v bb nominal operating supply range 6 30 v i bb total current consumption unloaded outputs 8 ma i bbs sleep current in v bb (note 7) unloaded outputs 100 a v dd v dd logic supply output voltage 4.75 5 5.25 v i load maximum output current 6 v v bb 8 v 15 ma 8 v v bb 30 v 50 ma i ddlim current limitation 150 ma i load_pd output current in power down mode 1 ma power on reset (por) (note 10) v ddh v dd internal por comparator threshold v dd rising 3.85 4.20 4.55 v v ddl internal por comparator threshold v dd falling 3.85 v v ddhys hysteresis between v ddh and v ddl 0.10 0.35 0.60 v motor driver i mdmax,peak motxp motxn motyp motyn max peak current through motor coil t j = ? 40 c 1600 ma i mdabs absolute error on coil current t j = 125 c ? 10 10 % i mdrel error on current ratio i coilx /i coily ? 7 7 % i set_tc1 temperature coefficient of coil current set ? level, cur[4:0] = 0...27 t j 160 c ? 240 ppm/k i set_tc2 temperature coefficient of coil current set ? level, cur[4:0] = 28...31 t j 160 c ? 490 ppm/k r hs on ? resistance high ? side driver, (note 9) cur[4:0] = 0...31 v bb = 12 v, t j = 27 c 0.45 0.56 v bb = 12 v, t j = 160 c 0.94 1.25 r ls3 on ? resistance low ? side driver, (note 9) cur[4:0] = 23...31 v bb = 12 v, t j = 27 c 0.45 0.56 v bb = 12 v, t j = 160 c 0.94 1.25 r ls2 on ? resistance low ? side driver, (note 9) cur[4:0] = 16...22 v bb = 12 v, t j = 27 c 0.90 1.2 v bb = 12 v, t j = 160 c 1.9 2.5 r ls1 on ? resistance low ? side driver, (note 9) cur[4:0] = 9...15 v bb = 12 v, t j = 27 c 1.8 2.3 v bb = 12 v, t j = 160 c 3.8 5.0 r ls0 on ? resistance low ? side driver, (note 9) cur[4:0] = 0...8 v bb = 12 v, t j = 27 c 3.6 4.5 v bb = 12 v, t j = 160 c 7.5 10 i mpd pulldown current hiz mode 1 ma digital inputs i leak di, clk nxt, dir clr, cs input leakage (note 8) t j = 160 c 0.5 a v il logic low threshold 0 0.75 v v ih logic high threshold 2.20 v dd v r pd_clr clr internal pulldown resistor 120 280 k r pd_tst tst0 internal pulldown resistor 3 8 k 6. current with oscillator running, all analogue cells active, spi communication and nxt pulses applied. no floating inputs. gua ranteed by design. 7. current with all analogue cells in power down. logic is powered but no clocks running. all outputs unloaded, no inputs floati ng. 8. not valid for pins with internal pulldown resistor 9. characterization data only 10. por is derived from v dd . for proper por operation v bb needs to be minimal v bb_min .
amis ? 30522, NCV70522 http://onsemi.com 7 table 5. dc parameters (the dc parameters are given for v bb and temperature in their operating ranges unless otherwise specified) convention: currents flowing in the circuit are defined as positive. symbol unit max typ min remark/test conditions parameter pin(s) digital outputs v ol do, err logic low level open drain i ol = 5 ma 0.30 v thermal warning and shutdown t tw thermal warning 138 145 152 c t tsd (notes 11, 12) thermal shutdown t tw + 20 c charge pump v cp vcp output voltage 6 v v bb 14 v 2 * v bb ? 2.5 v 14 v < v bb 30 v v bb + 10 v bb + 15 c buffer external buffer capacitor 180 220 470 nf c pump cpp cpn external pump capacitor 180 220 470 nf package thermal resistance values rth ja nqfp thermal resistance junction ? to ? ambient simulated conform jedec jesd ? 51, (2s2p) 30 k/w rth jp thermal resistance junction ? to ? exposed pad 0.95 k/w speed and load angle output v out sla output voltage range 0.2 v dd ? 0.2 v v off output offset sla pin slag = 0 ? 50 50 mv slag = 1 ? 30 30 mv g sla gain of sla pin = v bemf / v coil slag = 0 0.5 slag = 1 0.25 r out output resistance sla pin 0.23 1.0 k c load load capacitance sla pin 50 pf 11. no more than 100 cumulative hours in life time above t tw 12. thermal shutdown is derived from thermal warning
amis ? 30522, NCV70522 http://onsemi.com 8 table 6. ac parameters (the ac parameters are given for v bb and temperature in their operating ranges) symbol pin(s) parameter remark/test conditions min typ max unit internal oscillator f osc frequency of internal oscillator 3.6 4.0 4.4 mhz motordriver f pwm motxx pwm frequency frequency depends only on internal oscillator 20.8 22.8 24.8 khz double pwm frequency 41.6 45.6 49.6 khz f d pwm jitter depth (note 13) 10 % f pwm tb rise motxx turn ? on voltage slope, 10% to 90% (note 13) emc[1:0] = 00 150 v/ s emc[1:0] = 01 100 v/ s emc[1:0] = 10 50 v/ s emc[1:0] = 11 25 v/ s tb fall motxx turn ? off voltage slope, 90% to 10% (note 13) emc[1:0] = 00 150 v/ s emc[1:0] = 01 100 v/ s emc[1:0] = 10 50 v/ s emc[1:0] = 11 25 v/ s digital outputs t h2l do err output falltime from v inh to v inl capacitive load 400 pf and pullup resistor of 1.5 k 50 ns charge pump f cp cpn cpp charge pump frequency 250 khz t cpu motxx startup time of charge pump (note 14) spec external components 5.0 ms clr function t clr clr minimum time for hard reset 100 s nxt function t nxt_hi nxt nxt minimum, high pulse width see figure 4 2.0 s t nxt_lo nxt minimum, low pulse width see figure 4 2.0 s t dir_set nxt hold time, following change of dir see figure 4 2.0 s t dir_hold nxt hold time, before change of dir see figure 4 2.0 s power up t pu porb/ wd power ? up time v bb = 12 v, i load = 50 ma, c load = 220 nf 110 s t pd power ? down time external conditions ms t por reset duration 100 ms t rf reset filter time 1.0 s watchdog t wdto watchdog time out interval 32 512 ms t wdpr prohibited watchdog acknowledge delay 2.0 ms 13. characterization data only 14. guaranteed by design.
amis ? 30522, NCV70522 http://onsemi.com 9 dir nxt valid figure 4. nxt ? input timing diagram t dir_set t dir_hold 0.5 v cc t nxt_hi t nxt_lo table 7. spi timing parameters symbol parameter min typ max unit t clk spi clock period 1 s t clk_high spi clock high time 100 ns t clk_low spi clock low time 100 ns t set_di di setup time, valid data before rising edge of clk 50 ns t hold_di di hold time, hold data after rising edge of clk 50 ns t csb_high cs high time 2.5 s t set_csb cs setup time, cs low before rising edge of clk 100 ns t set_clk clk setup time, clk low before rising edge of cs 100 ns figure 5. spi timing cs 0.8 v cc 0.2 v cc 0.2 v cc 0.2 v cc 0.2 v cc 0.8 v cc t clk t set_clk t set_csb t set_di t clk_hi t clk_lo t hold_di
amis ? 30522, NCV70522 http://onsemi.com 10 typical application schematic dir nxt do di clk clr sla amis ? 30522/ 100 nf 100 nf 100 nf 100 nf vdd vbb vbb vcp cpn cpp motxp motxn motyp motyn 220 nf r 3 r 2 c 4 c 2 c 3 c 6 c 7 m c 5 tsto gnd c 8 r 1 + c 1 cs err figure 6. typical application schematic amis ? 30522/NCV70522 5 4 31 2 3 13 12 6 7 11 9 10 25,26 21,22 15,16 19,20 NCV70522 1, 8 17, 18 23, 24 30 29 32 14 27 c 220 nf 100 f v bat 28 por /wd r 4 d 1 table 8. external components list and description component function typ. value tolerance unit c 1 v bb buffer capacitor (low esr < 1 ) 100 ? 20 +80% f c 2 , c 3 v bb decoupling block capacitor 100 ? 20 +80% nf c 4 v dd buffer capacitor 220 20% nf c 5 v dd buffer capacitor 100 20% nf c 6 charge ? pump buffer capacitor 220 20% nf c 7 charge ? pump pumping capacitor 220 20% nf c 8 low pass filter sla 1 20% nf r 1 low pass filter sla 5.6 1% k r 2 , r 3 pullup resistor open drain output 4.7 1% k d 1 reverse protection diode murd530
amis ? 30522, NCV70522 http://onsemi.com 11 functional description h ? bridge drivers a full h ? bridge is integrated for each of the two stator windings. each h ? bridge consists of two low ? side and two high ? side n ? type mosfet switches. writing logic ?0? in bit disables all drivers (high ? impedance). writing logic ?1? in this bit enables both bridges and current can flow in the motor stator windings. in order to avoid large currents through the h ? bridge switches, it is guaranteed that the top ? and bottom switches of the same half ? bridge are never conductive simultaneously (interlock delay). a two ? stage protection against shorts on motor lines is implemented. in a first stage, the current in the driver is limited. secondly, when excessive voltage is sensed across the transistor, the transistor is switched ? off. in order to reduce the radiated/conducted emission, voltage slope control is implemented in the output switches. the output slope is defined by the gate ? drain capacitance of output transistor and the (limited) current that drives the gate. there are two trimming bits for slope control (see table 12 spi control parameter overview emc[1:0]). the power transistors are equipped with so ? called ?active diodes?: when a current is forced through the transistor switch in the reverse direction, i.e. from source to drain, then the transistor is switched on. this ensures that most of the current flows through the channel of the transistor instead of through the inherent parasitic drain ? bulk diode of the transistor. depending on the desired current range and the micro ? step position at hand, the r ds(on) of the low ? side transistors will be adapted such that excellent current ? sense accuracy is maintained. the r ds(on) of the high ? side transistors remain unchanged, see also the dc ? parameter table for more details. pwm current control a pwm comparator compares continuously the actual winding current with the requested current and feeds back the information to a digital regulation loop. this loop then generates a pwm signal, which turns on/off the h ? bridge switches. the switching points of the pwm duty ? cycle are synchronized to the on ? chip pwm clock. the frequency of the pwm controller can be doubled to reduce the over ? all current ? ripple with a factor of two. to further reduce the emission, an artificial jitter can be added to the pwm frequency. (see table 12, spi control register 1). the pwm frequency will not vary with changes in the supply voltage. also variations in motor ? speed or load ? conditions of the motor have no effect. there are no external components required to adjust the pwm frequency. automatic forward & slow ? fast decay the pwm generation is in steady ? state using a combination of forward and slow ? decay. the absence of fast ? decay in this mode, guarantees the lowest possible current ? ripple ?by design?. for transients to lower current levels, fast ? decay is automatically activated to allow high ? speed response. the selection of fast or slow decay is completely transparent for the user and no additional parameters are required for operation. icoil 0 t forward & slow decay actual value set value figure 7. forward & slow/fast decay pwm t pwm forward & slow decay fast decay & forward
amis ? 30522, NCV70522 http://onsemi.com 12 automatic duty cycle adaptation in case the supply voltage is lower than 2*bemf, then the duty cycle of the pwm is adapted automatically to >50% to maintain the requested average current in the coils. this process is completely automatic and requires no additional parameters for operation. actual value duty cycle < 50% duty cycle < 50% t icoil set value figure 8. automatic duty cycle adaptation duty cycle > 50% t pwm step translator step mode the step translator provides the control of the motor by means of spi register stepmode: sm[2:0], spi register dircntrl and input pins dir and nxt. it is translating consecutive steps in corresponding currents in both motor coils for a given stepmode. one out of 7 possible stepping modes can be selected through spi ? bits sm[2:0] (table 12). after power ? on or hard reset, the coil ? current translator is set to the default 1/32 micro ? stepping at position ?0?. upon changing the step mode, the translator jumps to position 0* of the corresponding stepping mode. when remaining in the same step mode, subsequent translator positions are all in the same column and increased or decreased with 1. table 10 lists the output current vs. the translator position. as shown in figure 9 the output current ? pairs can be projected approximately on a circle in the (i x ,i y ) plane. there are however two exceptions: uncompensated half step and full step. in these stepmodes the currents are not regulated to a fraction of i max but are in all intermediate steps regulated at 100%. in the (i x ,i y ) plane the current ? pairs are projected on a square. t able 9 lists the output current vs. the translator position for these cases. table 9. square translator table for full step and uncompensated half step msp[6:0] stepmode ( sm[2:0] ) % of i max 101 110 coil x coil y uncompensated half ? step full step 000 0000 0* ? 0 100 001 0000 1 1 100 100 010 0000 2 ? 100 0 011 0000 3 2 100 ? 100 100 0000 4 ? 0 ? 100 101 0000 5 3 ? 100 ? 100 110 0000 6 ? ? 100 0 111 0000 7 0 ? 100 100
amis ? 30522, NCV70522 http://onsemi.com 13 table 10. circular translator table msp[6:0] stepmode (sm[2:0]) % of i max 000 001 010 011 100 coil x coil y 1/32 1/16 1/8 1/4 1/2 000 0000 ?0? 0* 0* 0* 0* 0 100 000 0001 1 ? ? ? ? 3.5 98.8 000 0010 2 1 ? ? ? 8.1 97.7 000 0011 3 ? ? ? ? 12.7 96.5 000 0100 4 2 1 ? ? 17.4 95.3 000 0101 5 ? ? ? ? 22.1 94.1 000 0110 6 3 ? ? ? 26.7 93 000 0111 7 ? ? ? ? 31.4 91.8 000 1000 8 4 2 1 ? 34.9 89.5 000 1001 9 ? ? ? ? 38.3 87.2 000 1010 10 5 ? ? ? 43 84.9 000 1011 11 ? ? ? ? 46.5 82.6 000 1100 12 6 3 ? ? 50 79 000 1101 13 ? ? ? ? 54.6 75.5 000 1110 14 7 ? ? ? 58.1 72.1 000 1111 15 ? ? ? ? 61.6 68.6 001 0000 16 8 4 2 1 65.1 65.1 001 0001 17 ? ? ? ? 68.6 61.6 001 0010 18 9 ? ? ? 72.1 58.1 001 0011 19 ? ? ? ? 75.5 54.6 001 0100 20 10 5 ? ? 79 50 001 0101 21 ? ? ? ? 82.6 46.5 001 0110 22 11 ? ? ? 84.9 43 001 0111 23 ? ? ? ? 87.2 38.3 001 1000 24 12 6 3 ? 89.5 34.9 001 1001 25 ? ? ? ? 91.8 31.4 001 1010 26 13 ? ? ? 93 26.7 001 1011 27 ? ? ? ? 94.1 22.1 001 1100 28 14 7 ? ? 95.3 17.4 001 1101 29 ? ? ? ? 96.5 12.7 001 1110 30 15 ? ? ? 97.7 8.1 001 1111 31 ? ? ? ? 98.8 3.5 010 0000 32 16 8 4 2 100 0 010 0001 33 ? ? ? ? 98.8 ? 3.5 010 0010 34 17 ? ? ? 97.7 ? 8.1 010 0011 35 ? ? ? ? 96.5 ? 12.7 010 0100 36 18 9 ? ? 95.3 ? 17.4 010 0101 37 ? ? ? ? 94.1 ? 22.1 010 0110 38 19 ? ? ? 93 ? 26.7 010 0111 39 ? ? ? ? 91.8 ? 31.4 010 1000 40 20 10 5 ? 89.5 ? 34.9 010 1001 41 ? ? ? ? 87.2 ? 38.3 010 1010 42 21 ? ? ? 84.9 ? 43 010 1011 43 ? ? ? ? 82.6 ? 46.5 010 1100 44 22 11 ? ? 79 ? 50 010 1101 45 ? ? ? ? 75.5 ? 54.6 010 1110 46 23 ? ? ? 72.1 ? 58.1 010 1111 47 ? ? ? ? 68.6 ? 61.6 011 0000 48 24 12 6 3 65.1 ? 65.1 011 0001 49 ? ? ? ? 61.6 ? 68.6 011 0010 50 25 ? ? ? 58.1 ? 72.1 011 0011 51 ? ? ? ? 54.6 ? 75.5 011 0100 52 26 13 ? ? 50 ? 79 011 0101 53 ? ? ? ? 46.5 ? 82.6 011 0110 54 27 ? ? ? 43 ? 84.9 011 0111 55 ? ? ? ? 38.3 ? 87.2 011 1000 56 28 14 7 ? 34.9 ? 89.5 011 1001 57 ? ? ? ? 31.4 ? 91.8 011 1010 58 29 ? ? ? 26.7 ? 93 011 1011 59 ? ? ? ? 22.1 ? 94.1 011 1100 60 30 15 ? ? 17.4 ? 95.3 011 1101 61 ? ? ? ? 12.7 ? 96.5 011 1110 62 31 ? ? ? 8.1 ? 97.7
amis ? 30522, NCV70522 http://onsemi.com 14 table 10. circular translator table msp[6:0] % of i max stepmode (sm[2:0]) msp[6:0] coil y coil x 100 011 010 001 000 msp[6:0] coil y coil x 1/2 1/4 1/8 1/16 1/32 011 1111 63 ? ? ? ? 3.5 ? 98.8 100 0000 64 32 16 8 4 0 ? 100 100 0001 65 ? ? ? ? ? 3.5 ? 98.8 100 0010 66 33 ? ? ? ? 8.1 ? 97.7 100 0011 67 ? ? ? ? ? 12.7 ? 96.5 100 0100 68 34 17 ? ? ? 17.4 ? 95.3 100 0101 69 ? ? ? ? ? 22.1 ? 94.1 100 0110 70 35 ? ? ? ? 26.7 ? 93 100 0111 71 ? ? ? ? ? 31.4 ? 91.8 100 1000 72 36 18 9 ? ? 34.9 ? 89.5 100 1001 73 ? ? ? ? ? 38.3 ? 87.2 100 1010 74 37 ? ? ? ? 43 ? 84.9 100 1011 75 ? ? ? ? ? 46.5 ? 82.6 100 1100 76 38 19 ? ? ? 50 ? 79 100 1101 77 ? ? ? ? ? 54.6 ? 75.5 100 1110 78 39 ? ? ? ? 58.1 ? 72.1 100 1111 79 ? ? ? ? ? 61.6 ? 68.6 101 0000 80 40 20 10 5 ? 65.1 ? 65.1 101 0001 81 ? ? ? ? ? 68.6 ? 61.6 101 0010 82 41 ? ? ? ? 72.1 ? 58.1 101 0011 83 ? ? ? ? ? 75.5 ? 54.6 101 0100 84 42 21 ? ? ? 79 ? 50 101 0101 85 ? ? ? ? ? 82.6 ? 46.5 101 0110 86 43 ? ? ? ? 84.9 ? 43 101 0111 87 ? ? ? ? ? 87.2 ? 38.3 101 1000 88 44 22 11 ? ? 89.5 ? 34.9 101 1001 89 ? ? ? ? ? 91.8 ? 31.4 101 1010 90 45 ? ? ? ? 93 ? 26.7 101 1011 91 ? ? ? ? ? 94.1 ? 22.1 101 1100 92 46 23 ? ? ? 95.3 ? 17.4 101 1101 93 ? ? ? ? ? 96.5 ? 12.7 101 1110 94 47 ? ? ? ? 97.7 ? 8.1 101 1111 95 ? ? ? ? ? 98.8 ? 3.5 110 0000 96 48 24 12 6 ? 100 0 110 0001 97 ? ? ? ? ? 98.8 3.5 110 0010 98 49 ? ? ? ? 97.7 8.1 110 0011 99 ? ? ? ? ? 96.5 12.7 110 0100 100 50 25 ? ? ? 95.3 17.4 110 0101 101 ? ? ? ? ? 94.1 22.1 110 0110 102 51 ? ? ? ? 93 26.7 110 0111 103 ? ? ? ? ? 91.8 31.4 110 1000 104 52 26 13 ? ? 89.5 34.9 110 1001 105 ? ? ? ? ? 87.2 38.3 110 1010 106 53 ? ? ? ? 84.9 43 110 1011 107 ? ? ? ? ? 82.6 46.5 110 1100 108 54 27 ? ? ? 79 50 110 1101 109 ? ? ? ? ? 75.5 54.6 110 1110 110 55 ? ? ? ? 72.1 58.1 110 1111 111 ? ? ? ? ? 68.6 61.6 111 0000 112 56 28 14 7 ? 65.1 65.1 111 0001 113 ? ? ? ? ? 61.6 68.6 111 0010 114 57 ? ? ? ? 58.1 72.1 111 0011 115 ? ? ? ? ? 54.6 75.5 111 0100 116 58 29 ? ? ? 50 79 111 0101 117 ? ? ? ? ? 46.5 82.6 111 0110 118 59 ? ? ? ? 43 84.9 111 0111 119 ? ? ? ? ? 38.3 87.2 111 1000 120 60 30 15 ? ? 34.9 89.5 111 1001 121 ? ? ? ? ? 31.4 91.8 111 1010 122 61 ? ? ? ? 26.7 93 111 1011 123 ? ? ? ? ? 22.1 94.1 111 1100 124 62 31 ? ? ? 17.4 95.3 111 1101 125 ? ? ? ? ? 12.7 96.5 111 1110 126 63 ? ? ? ? 8.1 97.7 111 1111 127 ? ? ? ? ? 3.5 98.8
amis ? 30522, NCV70522 http://onsemi.com 15 start = 0 step 1 step 2 step 3 start = 0 step 1 step 2 step 3 start = 0 step 1 step 2 step 3 figure 9. translator table: circular and square 1/4th micro step sm[2:0] = 011 uncompensated half step sm[2:0] = 101 full step sm[2:0] = 110 i y i y i y i x i x i x direction the direction of rotation is selected by means of following combination of the dir input pin and the spi ? controlled direction bit as illustrated in table 12. nxt input changes on the nxt input will move the motor current one step up/down in the translator table (even when the motor is disabled). depending on the nxt ? polarity bit (see table 12), the next step is initiated either on the rising edge or the falling edge of the nxt input. translator position the translator position can be read in spi status register 3. this is a 7 ? bit number equivalent to the 1/32th micro ? step from table 10: ?circular translator table? above. the translator position is updated immediately following a nxt trigger. nxt update translator position update translator position figure 10. translator position timing diagram synchronization of step mode and nxt input when step mode is re ? programmed to another resolution, (figure 11), this is put in effect immediately upon the first arriving ?nxt? input. if the micro ? stepping resolution is increased, the coil currents will be regulated to the nearest micro ? step, according to the fixed grid of the increased resolution. if however the micro ? stepping resolution is decreased, then it is possible to introduce an offset (or phase shift) in the micro ? step translator table. if the step resolution is decreased at a translator table position that is shared both by the old and new resolution setting, then the offset is zero and micro ? stepping proceeds according to the translator table. if the translator position is not shared both by the old and new resolution setting, then the micro ? stepping proceeds with an offset relative to the translator table (see figure 11 right hand side).
amis ? 30522, NCV70522 http://onsemi.com 16 dir dir nxt1 nxt2 nxt3 nxt4 halfstep endpos 1/4th step change from lower to higher resolution startpos dir nxt1 nxt2 nxt3 dir endpos halfstep change from higher to lower resolution startpos figure 11. nxt ? step ? mode synchronization left: change from lower to higher resolution. the left ? hand side depicts the ending half ? step position during which a new step mode res- olution was programmed. the right ? hand side diagram shows the effect of subsequent nxt commands on the micro ? step position. right: change from higher to lower resolution. the left ? hand side depicts the ending micro ? step position during which a new step mode resolution was programmed. the right ? hand side diagram shows the effect of subsequent nxt commands on the half ? step position. note: it is advised to reduce the micro ? stepping resolution only at micro ? step positions that overlap with desired micro ? step positions of the new resolution. i y i x i y i x i y i x i y i x 1/8th step programmable peak ? current the amplitude of the current waveform in the motor coils (coil peak current = i max ) is adjusted by means of an spi parameter ?cur[4:0]? (table 14 ). whenever this parameter is changed, the coil ? currents will be updated immediately at the next pwm period. figure 12 presents the peak ? current and current ranges in conjunction to the current setting (cur[4:0]). peak current ipeak (cur[4:0] = 1 1111) ipeak (cur[4:0] = 10110) ipeak (cur[4:0] = 01111) ipeak (cur[4:0] = 01000) 0 8 15 22 31 cur[4:0] current range 3 cur = 23 ? > 31 current range 2 cur = 16 ? > 22 current range 1 cur = 9 ? > 15 current cur = 0 ? > 8 figure 12. programmable peak ? current overview range 0 speed and load ? angle output the sla ? pin provides an output voltage that indicates the level of the back ? e.m.f. voltage of the motor. this back ? e.m.f. voltage is sampled during every so ? called ?coil current zero crossings?. per coil, 2 zero ? current positions
amis ? 30522, NCV70522 http://onsemi.com 17 exist per electrical period, yielding in total 4 zero ? current observation points per electrical period. figure 13. principle of bemf measurement current decay zero current voltage transient zoom previous micro ? step coil current zero crossing next micro ? step t i coil v bemf i coil v coil v bb |v bemf | t t because of the relatively high re ? circulation currents in the coil during current decay, the coil voltage v coil shows a transient behavior. as this transient is not always desired in application software, two operating modes can be selected by means of the bit (see ?sla ? transparency? in table 12). the sla pin shows in ?transparent mode? full visibility of the voltage transient behavior. this allows a sanity ? check of the speed ? setting versus motor operation and characteristics and supply voltage levels. if the bit ?slat? is cleared, then only the voltage samples at the end of each coil current zero crossing are visible on the sla ? pin. because the transient behavior of the coil voltage is not visible anymore, this mode generates smoother back e.m.f. input for post ? processing, e.g. by software. in order to bring the sampled back e.m.f. to a descent output level (0 v to 5 v), the sampled coil voltage v coil is divided by 2 or by 4. this divider is set through a spi bit . (see table 12) the following drawing illustrates the operation of the sla ? pin and the transparency ? bit. ?pwmsh? and ?icoil=0? are internal signals that define together with slat the sampling and hold moments of the coil voltage.
amis ? 30522, NCV70522 http://onsemi.com 18 pwmsh slat sla ? pin last retained retain last sample previous output is buf ssh sh ch csh slat not (icoil=0) icoil=0 pwmsh sla ? pin div2 div4 t t figure 14. timing diagram of sla ? pin slat = 1 => sla ? pin is ?transparent? during v bemf sampling @ coil current zero crossing. sla ? pin is updated ?real ? time?. slat = 0 => sla ? pin is not ?transparent? during v bemf sampling @ coil current zero crossing. sla ? pin is updated when leaving current ? less state. v coil v coil v bemf sample is kept at sla pin icoil=0 warning, error detection and diagnostics feedback thermal warning and shutdown when junction temperature rises above t tw , the thermal warning bit is set (t able 16 spi status register 0). if junction temperature increases above thermal shutdown level, then the circuit goes in ?thermal shutdown? mode ( ) and all driver transistors are disabled (high impedance) (table 16 spi status register 2). the conditions to reset flag is to be at a temperature lower than t tw and to clear the flag by reading it using any spi read command. overcurrent detection the overcurrent detection circuit monitors the load current in each activated output stage. if the load current exceeds the overcurrent detection threshold, then the overcurrent flag is set and the drivers are switched off to reduce the power dissipation and to protect the integrated circuit. each driver transistor has an individual detection bit in the table 16 spi status registers 1 and spi status register 2 ( and ). error condition is latched and the microcontroller needs to clear the status bits to reactivate the drivers. note : successive reading the spi status registers 1 and 2 in case of a short circuit condition, may lead to damage to the drivers. open coil detection open coil detection is based on the observation of 100% duty cycle of the pwm regulator. if in a coil 100% duty cycle is detected for longer than 32 ms the appropriate status bit in the spi status register is set ( or ). (table 16: spi status register 0). when the resistance of a motor coil is very large and the battery voltage is low, it can happen that the motor driver is not able to deliver the requested current to the motor. under these conditions the pwm controller duty cycle will be 100% and after 32 ms, the error pin and , will flag this situation (motor current is kept alive). this feature can be used to test if the operating conditions (supply voltage, motor coil resistance) still allow reaching the requested coil ? current or else the coil ? current should be reduced.
amis ? 30522, NCV70522 http://onsemi.com 19 charge pump failure the charge pump is an important circuit that guarantees low r ds(on) for all drivers, especially for low supply voltages. if the supply voltage is too low or external components are not properly connected to guarantee r ds(on) of the drivers, then the bit is set in the spi status register 0. also after power ? on ? reset the charge pump voltage will need some time to exceed the required threshold. during that time will be set to ?1?. error output this is an open drain digital output to flag a problem to the external microcontroller. the signal on this output is active low and the logic combination of: not(err ) = or or or or or logic supply regulator the 522 has an on ? chip 5 v low ? drop regulator with external capacitor to supply the digital part of the chip, some low ? voltage analog blocks and external circuitry. the voltage level is derived from an internal bandgap reference. to calculate the available drive ? current for external circuitry, the specified i load should be reduced with the consumption of internal circuitry (unloaded outputs) and the loads connected to logic outputs. see table 5. power ? on reset (por) function the open drain output pin por /wd provides an ?active low? reset for external purposes. at powerup of amis ? 30522/NCV70522, this pin will be kept low for some time to reset for example an external microcontroller. a small analog filter avoids resetting due to spikes or noise on the v dd supply. figure 15. power ? on ? reset timing diagram vbb vdd t t v ddh v ddl por /wd pin t pu t pd < t rf t por t rf watchdog function the watchdog function is enabled/disabled through bit (table 13). once this bit has been set to ?1? (watchdog enable), the microcontroller needs to re ? write this bit to clear an internal timer before the watchdog timeout interval expires. in case the timer is activated and wden is acknowledged too early (before t wdpr ) or not within the interval (after t wdto ), then a reset of the microcontroller will occur through por /wd pin. in addition, a warm/cold boot bit is available in table 16 for further processing when the external microcontroller is alive again.
amis ? 30522, NCV70522 http://onsemi.com 20 vbb vdd t t enable wd acknowledge wd wd timer t t figure 16. watchdog timing diagram v ddh t pu t por t dspi por /wd pin t wdto t por t wdrd = t wdpr or = t wdto > t wdpr and < t wdto note: t dspi is the time needed by the external microcontroller to shift ? in the bit after a power ? up. the duration of the watchdog timeout interval is programmable through the wdt[3:0] bits. the timing is given in figure 16. clr pin (=hard reset) logic 0 on clr pin allows normal operation of the chip. to reset the complete digital inside the 522, the input clr needs to be pulled to logic 1 during minimum time given by t clr . (see ac parameters) this reset function clears all internal registers without the need of a power ? cycle, except in sleep mode. the operation of all analog circuits is depending on the reset state of the digital, charge pump remains active. logic 0 on clr pin resumes normal operation again. the voltage regulator remains functional during and after the reset and the por /wd pin is not activated. watchdog function is reset completely. sleep mode the bit in spi control register 2 is provided to enter a so ? called ?sleep mode?. this mode allows reduction of current ? consumption when the motor is not in operation. the effect of sleep mode is as follows: ? the drivers are put in hiz ? all analog circuits are disabled and in low ? power mode ? all internal registers are maintaining their logic content ? nxt and dir inputs are ignored ? spi communication remains possible (slight current increase during spi communication) ? oscillator and digital clocks are silent, except during spi communication normal operation is resumed after writing logic ?0? to bit . a start ? up time is needed for the charge pump to stabilize. after this time, nxt commands can be issued. when the device is in sleep mode and v bb becomes lower than v bb_min the device might reset.
amis ? 30522, NCV70522 http://onsemi.com 21 spi interface the serial peripheral interface (spi) allows an external microcontroller (master) to communicate with the 522. the implemented spi block is designed to interface directly with numerous micro ? controllers from several manufacturers. the 522 acts always as a slave and cannot initiate any transmission. t he operation of the device is configured and controlled by means of spi registers which are observable for read and/or write from the master. spi transfer format and pin signals during a spi transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). a serial clock line (clk) synchronizes shifting and sampling of the information on the two serial data lines (do and di). do signal is the output from the slave (522), and di signal is the output from the master. a chip select line (cs ) allows individual selection of a slave spi device in a multiple ? slave system. the cs line is active low. if the 522 is not selected, do is pulled up with the external pullup resistor. since 522 operates as a slave in mode 0 (cpol = 0; cpha = 0) it always clocks data out on the falling edge and samples data in on rising edge of clock. the master spi port must be configured in mode 0 too, to match this operation. the spi clock idles low between the transferred bytes. the diagram below is both a master and a slave timing diagram since clk, do and di pins are directly connected between the master and the slave. di msb clk 1 2 3 4 5 6 7 8 do #clk cycle msb lsb lsb 6 54321 6 54321 figure 17. timing diagram of a spi transfer cs note: at the falling edge of the eighth clock pulse the data ? out shift register is updated with the content of the addressed internal spi register. the internal spi registers are updated at the first rising edge of the 522 system clock when cs = high. transfer packet serial data transfer is assumed to follow msb first rule. the transfer packet contains one or more bytes. lsb data command and spi register address cmd2 cmd1 cmd0 addr4 addr3 addr2 addr1 addr0 d7 d6 d5 d4 d3 d2 d1 d0 msb lsb msb byte 1 byte 2 command spi register address figure 18. spi transfer packet byte 1 contains the command and the spi register address and indicates to the 522 the chosen type of operation and addressed register. byte 2 contains data, or sent from the master in a write operation, or received from the 522 in a read operation. two command types can be distinguished in the communication between master and 522: ? read from spi register with address addr[4:0]: cmd[2:0] = ?000? ? write to spi register with address addr[4:0]: cmd[2:0] = ?100?
amis ? 30522, NCV70522 http://onsemi.com 22 read operation if the master wants to read data from status or control registers, it initiates the communication by sending a read command. this read command contains the address of the spi register to be read out. at the falling edge of the eighth clock pulse the data ? out shift register is updated with the content of the corresponding internal spi register. in the next 8 ? bit clock pulse train this data is shifted out via do pin. at the same time the data shifted in from di (master) should be interpreted as the following successive command or dummy data. figure 19. single read operation where data from spi register with address 1 is read by the master data from previous command or not valid after por or reset registers are updated with the internal status at the rising edge of the internal amis ? 30522/NCV70522 clock when cs = 1 read data from addr1 command or dummy old data or not valid data from addr1 command data data do di cs all 4 status registers (see spi registers) contain 7 data bits and an even parity check bit. the most significant bit (d7) represents a parity of d[6:0]. if the number of logical ones in d[6:0] is odd, the parity bit d7 equals ?1?. if the number of logical ones in d[6:0] is even then the parity bit d7 equals ?0?. this simple mechanism protects against noise and increases the consistency of the transmitted data. if a parity check error occurs it is recommended to initiate an additional read command to obtain the status again. also the control registers can be read out following the same routine. control registers don?t have a parity check. the cs line is active low and may remain low between successive read commands as illustrated in figure 21. there is however one exception. in case an error condition is latched in one of status registers (see spi registers) the err pin is activated. (see the ?error output? section). this signal flags a problem to the external microcontroller. by reading the status registers information, the root cause of the problem can be determined. after this read operation the status registers are cleared. because the status registers and err pin (see spi registers) are only updated by the internal system clock when the cs line is high, the master should force cs high immediately after the read operation. for the same reason it is recommended to keep the cs line high always when the spi bus is idle. write operation if the master wants to write data to a control register it initiates the communication by sending a write command. this contains the address of the spi register to write to. the command is followed with a data byte. this incoming data will be stored in the corresponding control register after cs goes from low to high! amis ? 30522/ NCV70522 responds on every incoming byte by shifting out via do the data stored in the last received address. it is important that the writing action (command ? address and data) to the control register is exactly 16 bits long. if more or less bits are transmitted the complete transfer packet is ignored. a write command executed for a read ? only register (e.g. status registers) will not affect the addressed register and the device operation. because after a power ? on ? reset the initial address is unknown the data shifted out via do is not valid. data from previous command or not valid after por or reset do di cs write data to addr3 new data for addr3 old data or not valid old data from addr3 command data data data the new data is written into the corresponding internal register at the rising edge of cs figure 20. single write operation where data from the master is written in spi register with address 3
amis ? 30522, NCV70522 http://onsemi.com 23 examples of combined read and write operations in the following examples successive read and write operations are combined. in figure 21 the master first reads the status from register at addr4 and at addr5 followed by writing a control byte in control register at addr2. note that during the write command (in figures 20 and 21) the old data of the pointed register is returned at the moment the new data is shifted in. figure 21. two successive read commands followed by a write command command command command data data data data data do di cs data from previous command or not valid after por or reset read data from addr4 read data from addr5 write data to addr2 new data for addr2 old data or not valid data from addr4 data from addr5 old data from addr2 registers are updated with the internal status at the rising edge of the internal 522 clock when cs = 1 the new data is written into the corresponding internal register at the rising edge of cs after the write operation the master could initiate a read back command in order to verify if the data is correctly written, as illustrated in figure 22. during reception of the read command the old data is returned for a second time. only after receiving the read command the new data is transmitted. this rule also applies when the master device wants to initiate an spi transfer to read the status registers. because the internal system clock updates the status registers only when cs line is high, the first read out byte might represent old status information. command data data data data old data or not valid old data from addr2 old data from addr2 new data from addr2 do di cs figure 22. a write operation where data from the master is written in spi register with address 2 followed by a read back operation to verify a correct write operation data command write data to addr2 new data for addr2 read data from addr2 command or dummy registers are updated with the internal status at the rising edge of cs registers are updated with the in- ternal status at the rising edge of the internal 522 clock when cs = 1 data from previous command or not valid after por or reset note: the internal data ? out shift buffer of the amis ? 30522/NCV70522 is updated with the content of the selected spi register only at the last (every eighth) falling edge of the clk signal (see spi tr ansfer format and pin signals). as a result, new data for transmi ssion cannot be written to the shift buffer at the beginning of the transfer packet and the first byte shifted out might represent ol d data. table 11. spi control registers (all spi control registers have read/write access and default to ?0? after power ? on or hard reset) address content structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 crwd (00h) data wden wdt[3:0] 0 0 0 cr0 (01h) data sm[2:0] cur[4:0] cr1 (02h) data dirctrl nxtp ? ? pwmf pwmj emc[1:0] cr2 (03h) data moten slp slag slat ? ? ? ? where: r/w: read and write access reset: status after power ? on or hard reset wden: watchdog enable. writing ?0? to this bit will clear wd bit (see spi status register 0) wdt[3:0]: watchdog timeout interval
amis ? 30522, NCV70522 http://onsemi.com 24 table 12. spi control parameter overview symbol description status value wden watchdog enable. = 1 writing ?1? to this bit will enable the watchdog timer (if not enabled yet) or will clear this timer (if already enabled) = 0 writing ?0? to this bit will disable the watchdog dirctrl controls the direction of rotation (in combination with logic level on input dir) = 0 = 0 cw motion = 1 ccw motion = 1 = 0 ccw motion = 1 cw motion emc[1:0] turn on ? and turn ? off slopes (note 15) 00 very fast 01 fast 10 slow 11 very slow moten activates the motor driver outputs = 0 drivers disabled = 1 drivers enabled nxtp selects if nxt triggers on rising or falling edge = 0 trigger on rising edge = 1 trigger on falling edge pwmf enables doubling of the pwm frequency (note 15) = 0 default frequency = 1 double frequency pwmj enables jitter pwm = 0 jitter disabled = 1 jitter enabled sm[2:0] stepmode 000 1/32 micro step 001 1/16 micro step 010 1/8 micro step 011 1/4 micro step 100 1/2 compensated half step 101 1/2 uncompensated half step 110 full step 111 n.a. slag speed load angle gain setting = 0 gain = 0.5 = 1 gain = 0.25 slat speed load angle transparency bit = 0 sla is not transparent = 1 sla is transparent slp enables sleep mode = 0 active mode = 1 sleep mode 15. the typical values can be found in table 5: dc parameters and table 6: ac parameters
amis ? 30522, NCV70522 http://onsemi.com 25 wdt[3:0] selects the watchdog timeout interval. table 13. watchdog timeout interval as function of wdt[3:0] index wdt[3:0] t wdto (ms) 0 0 0 0 0 32 1 0 0 0 1 64 2 0 0 1 0 96 3 0 0 1 1 128 4 0 1 0 0 160 5 0 1 0 1 192 6 0 1 1 0 224 7 0 1 1 1 256 index wdt[3:0] t wdto (ms) 8 1 0 0 0 288 9 1 0 0 1 320 a 1 0 1 0 352 b 1 0 1 1 384 c 1 1 0 0 416 d 1 1 0 1 448 e 1 1 1 0 480 f 1 1 1 1 512 cur[4:0] selects imcmax peak. this is the peak or amplitude of the regulated current waveform in the motor coils. table 14. spi control parameter overview: current amplitude cur[4:0] current range (note 17) index cur[4:0] current (ma) (note 16) current range (note 17) index cur[4:0] current (ma) (note 16) 0 0 00000 33 2 16 10000 365 1 00001 64 17 10001 400 2 00010 95 18 10010 440 3 00011 104 19 10011 485 4 00100 115 20 10100 530 5 00101 126 21 10101 585 6 00110 138 22 10110 630 7 00111 153 3 23 10111 750 8 01000 166 24 11000 825 1 9 01001 190 25 11001 895 10 01010 205 26 11010 975 11 01011 230 27 11011 1065 12 01100 250 28 11100 1155 13 01101 275 29 11101 1245 14 01110 300 30 11110 1365 15 01111 325 31 11111 1480 16. typical current amplitude at t j = 125 c. 17. reducing the current over dif ferent current ranges might trigger overcurrent detection, please refer to dedicated application note for s olutions. spi status register description all 4 spi status registers have read access and are default to ?0? after power ? on or hard reset. table 15. spi status registers address content structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access r r r r r r r r reset 0 0 0 0 0 0 0 0 sr0 04h data not latched par tw cpfail wd openx openy ? ? sr1 05h data is latched par ovcxpt ovcxpb ovcxnt ovcxnb ? ? ? sr2 06h data is latched par ovcypt ovcypb ovcyynt ovcynb tsd ? ? sr3 07h data not latched par msp[6:0] where: r: read only mode access reset: status after power ? on or hard reset par: parity check
amis ? 30522, NCV70522 http://onsemi.com 26 table 16. spi status flags overview mnemonic flag length (bit) related spi register comment reset state cpfail charge pump failure 1 status register 0 ?0? = no failure ?1? = failure: indicates that the charge pump does not reach the required voltage level. ?0? wd watchdog event 1 status register 0 this bit indicates the watchdog timer has not been cleared properly in time. if the master reads that wd is set to ?1? after reset, it means that a watchdog re- set occurred (warm boot) instead of power ? on ? reset (cold boot). wd bit will be cleared only when the master writes ?0? to wden bit. ?0? msp[6:0] micro step position 7 status register 3 translator micro step position ?0000000? openx open coil x 1 status register 0 ?1? = open coil detected ?0? openy open coil y 1 status register 0 ?1? = open coil detected ?0? ovcxnb overcurrent at mot xn terminal; b ottom transistor 1 status register 1 ?0? = no failure ?1? = failure: indicates that overcurrent is detected at bottom transistor xn ? terminal ?0? ovcxnt overcurrent at mot xn terminal; t op transistor 1 status register 1 ?0? = no failure ?1? = failure: indicates that overcurrent is detected at top transistor xn ? terminal ?0? ovcxpb overcurrent at mot xp terminal; b ottom transistor 1 status register 1 ?0? = no failure ?1? = failure: indicates that overcurrent is detected at bottom transistor xp ? terminal ?0? ovcxpt overcurrent at mot xp terminal; t op transistor 1 status register 1 ?0? = no failure ?1? = failure: indicates that overcurrent is detected at top transistor xp ? terminal ?0? ovcynb overcurrent at mot yn terminal; b ottom transistor 1 status register 2 ?0? = no failure ?1? = failure: indicates that overcurrent is detected at bottom transistor yn ? terminal ?0? ovcynt overcurrent at mot yn terminal; t op transistor 1 status register 2 ?0? = no failure ?1? = failure: indicates that overcurrent is detected at top transistor yn ? terminal ?0? ovcypb overcurrent at mot yp terminal; b ottom transistor 1 status register 2 ?0? = no failure ?1? = failure: indicates that overcurrent is detected at bottom transistor yp ? terminal ?0? ovcypt overcurrent at mot yp terminal; t op transistor 1 status register 2 ?0? = no failure ?1? = failure: indicates that overcurrent is detected at top transistor yp ? terminal ?0? tsd thermal shutdown 1 status register 2 ?0? tw thermal warning 1 status register 0 ?0? wd watchdog event 1 status register 0 ?0? = no watchdog reset ?1? = watchdog reset occurred ?0?
amis ? 30522, NCV70522 http://onsemi.com 27 device ordering information part number ambient temperature range package type peak current shipping ? amis30522c5222rg ? 40 c to +125 c nqfp ? 32 (pb ? free) 1500 ma tape & reel amis30522c5222g ? 40 c to +125 c nqfp ? 32 (pb ? free) 1500 ma tube / tray NCV70522mn003r2g* ? 40 c to +125 c nqfp ? 32 (pb ? free) 1500 ma tape & reel NCV70522mn003g* ? 40 c to +125 c nqfp ? 32 (pb ? free) 1500 ma tube / tray ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *qualified for automotive applications.
amis ? 30522, NCV70522 http://onsemi.com 28 package dimensions nqfp ? 32, 7x7 case 560aa ? 01 issue o
amis ? 30522, NCV70522 http://onsemi.com 29 nqfp ? 32, 7x7 case 560aa ? 01 issue o on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 amis ? 30522/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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